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STK11C88
32Kx8 SoftStore nvSRAM FEATURES
* 25, 45 ns Read Access & R/W Cycle Time * Unlimited Read/Write Endurance * Pin Compatible with Industry Standard SRAMs * Software-initiated STORE and RECALL * Automatic RECALL to SRAM on Power Up * Unlimited RECALL Cycles * 1 Million Store Cycles * 100-Year Non-volatile Data Retention * Single 5.0V +10% Power Supply * Commercial and Industrial Temperatures * 28-pin 300-mil and 330-mil SOIC Packages (RoHS-Compliant) The Simtek STK11C88 is a 256Kb fast static RAM with a non-volatile Quantum Trap storage element included with each memory cell. The SRAM provides the fast access & cycle times, ease of use and unlimited read & write endurance of a normal SRAM. Data transfers under software control to the non-volatile storage cell (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). RECALL operations are also available under software control. The Simtek nvSRAM is the first monolithic nonvolatile memory to offer unlimited writes and reads. It is the highest performance, most reliable nonvolatile memory available.
DESCRIPTION
BLOCK DIAGRAM
QUANTUM TRAP 512 x 512 A5 A6 A7 A8 A9 A11 A12 A13 A14 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
ROW DECODER
STORE STATIC RAM ARRAY 512 X 512 RECALL
STORE/ RECALL CONTROL
SOFTWARE DETECT
A13 - A0
INPUT BUFFERS
COLUMN I/O COLUMN DEC
A 0 A 1 A 2 A 3 A 4 A10
G E W
This product conforms to specifications per the terms of Simtek standard warranty. The product has completed Simtek internal qualification testing and has reached production status.
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STK11C88
PIN CONFIGURATIONS
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14
(TOP)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
28 - Pin 300 mil SOIC 28 - Pin 330 mil SOIC
PIN DESCRIPTIONS
Pin Name A14-A0 DQ7-DQ0 E W G VCC VSS Input I/O Input Input Input Power Supply Power Supply I/O Description Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array Data: Bi-directional 8-bit data bus for accessing the nvSRAM Chip Enable: The active low E input selects the device Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high caused the DQ pins to tri-state. Power: 5.0V, +10% Ground
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STK11C88
ABSOLUTE MAXIMUM RATINGSa
Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Voltage on Input Relative to Ground . . . . . . . . . . . . . .-0.5V to 7.0V Voltage on Input Relative to VSS . . . . . . . . . . -0.6V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC + 0.5V) Temperature under Bias . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
DC CHARACTERISTICS
COMMERCIAL SYMBOL PARAMETER MIN MAX MIN MAX INDUSTRIAL UNITS
(VCC = 5.0V 10%)
NOTES
ICC1b ICC2c ICC3b ISB1d ISB2d IILK IOLK VIH VIL VOH VOL TA VCAP
Average VCC Current Average VCC Current during STORE Average VCC Current at tAVAV = 200ns 5V, 25C, Typical Average VCC Current (Standby, Cycling TTL Input Levels) VCC Standby Current (Standby, Stable CMOS Input Levels) Input Leakage Current Off-State Output Leakage Current Input Logic "1" Voltage Input Logic "0" Voltage Output Logic "1" Voltage Output Logic "0" Voltage Operating Temperature Storage Capacitance 0 61 2.2 VSS - .5 2.4
97 70 3 10 30 22 750
1 5
100 70 3 10 31 23 750
1 5
mA mA mA mA mA mA
A A A
tAVAV = 25ns tAVAV = 45ns All Inputs Don't Care, VCC = max W (V CC - 0.2V) All Others Cycling, CMOS Levels tAVAV = 25ns, E VIH tAVAV = 45ns, E VIH E (V CC - 0.2V) All Others VIN 0.2V or (VCC - 0.2V) VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G VIH All Inputs All Inputs IOUT = - 4mA IOUT = 8mA
VCC + .5 0.8
2.2 VSS - .5 2.4
VCC + .5 0.8
V V V
0.4 70 220 -40 61
0.4 85 220
V
C F
5 Volt rated, 68 F+20%, -10% Nom.
Note b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. Note c: ICC2 is the average current required for the duration of the STORE cycle (tSTORE ) . Note d: E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
5.0V
CAPACITANCEe
SYMBOL PARAMETER
(TA = 25C, f = 1.0MHz)
MAX UNITS CONDITIONS V = 0 to 3V V = 0 to 3V
480 Ohms OUTPUT 255 Ohms
CIN COUT
Input Capacitance Output Capacitance
5 7
pF pF
30 pF INCLUDING SCOPE AND FIXTURE
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
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STK11C88
SRAM READ CYCLES #1 & #2
SYMBOLS NO. PARAMETER #1, #2 Alt. MIN MAX MIN MAX
(VCC = 5.0V + 10%)
STK11C88-25 STK11C88-45 UNITS
1 2 3 4 5 6 7 8 9 10 11
tELQV tAVAVf, tELEHf tAVQVg tGLQV tAXQXg tELQX tEHQZh tGLQX tGHQZh tELICCHe tEHICCLd, e
tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS
Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold after Address Change Address Change or Chip Enable to Output Active Address Change or Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 0 0 5 5 25
25 45 25 10 5 5 10 0 10 0 25
45
ns ns
45 20
ns ns ns ns
15
ns ns
15
ns ns
45
ns
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected. Note h: Measured 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
tAVAV ADDRESS
5 3 2
tAVQV
DATA VALID
tAXQX DQ (DATA OUT)
SRAM READ CYCLE #2: E and G Controlledf
ADDR ESS t E LE H 1 tEL Q V
2 29
tEHAX 11 tEHI CC L 7 tEHQ Z
E
27
6 t ELQ X
G
t AV QV 4 t G L QV 9 tGH Q Z
3
8 tG L Q X DQ (D ATA OUT) 10 tELI CC H
DAT A VAL ID
AC T IVE
ICC
ST AND BY
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STK11C88
SRAM WRITE CYCLES #1 & #2 (VCC = 5.0V + 10%)
SYMBOLS NO. #1 #2 Alt. PARAMETER MIN MAX MIN MAX STK11C88-25 STK11C88-45 UNITS
12 13 14 15 16 17 18 19 20 21
tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX tWLQZh, i tWHQX
tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tAVEL tEHAX
tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW
Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Set-up to End of Write Data Hold after End of Write Address Set-up to End of Write Address Set-up to Start of Write Address Hold after End of Write Write Enable to Output Disable Output Active after End of Write
25 20 20 10 0 20 0 0 10 5
45 30 30 15 0 30 0 0 15 5
ns ns ns ns ns ns ns ns ns ns
Note i: Note j:
If W is low when E goes low, the outputs remain in the high-impedance state. E or W must be VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledj
12 tAVAV ADDRESS 14 tELWH E 17 tAVWH 13 tWLWH 15 tDVWH DATA IN 20 tWLQZ
PREVIOUS DATA DATA VALID
19 tWHAX
18 tAVWL W
16 tWHDX
DATA OUT
HIGH IMPEDANCE
21 tWHQX
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STK11C88
SRAM WRITE CYCLE #2: E Controlledj
12 tAVAV ADDRESS 18 tAVEL E 14 tELEH 19 tEHAX
17 tAVEH W
13 tWLEH 15 tDVEH 16 tEHDX
DATA VALID HIGH IMPEDANCE
DATA IN DATA OUT
AutoStoreTM INHIBIT/POWER-UP RECALL
SYMBOLS NO. Standard PARAMETER
(VCC = 5.0V + 10%)
STK11C88 UNITS NOTES MIN MAX
22 23 24 25
tRESTORE tSTORE VSWITCH VRESET
Power-up RECALL Duration
STORE Cycle Duration
550 10 4.0 4.5 3.6
s
k g
ms V V
Low Voltage Trigger Level Low Voltage Reset Level
Note k: tRESTORE starts from the time VCC rises above VSWITCH.
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STK11C88
AutoStoreTM INHIBIT/POWER-UP RECALL
VCC
5V 24 VSWITCH
25 VRESET
STORE INHIBIT
POWER-UP RECALL
22 tRESTORE
DQ (DATA OUT)
POWER-UP RECALL
BROWN OUT STORE INHIBIT NO RECALL (VCC DID NOT GO BELOW VRESET)
BROWN OUT STORE INHIBIT NO RECALL (VCC DID NOT GO BELOW VRESET)
BROWN OUT STORE INHIBIT RECALL WHEN VCC RETURNS ABOVE VSWITCH
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STK11C88
SOFTWARE STORE/RECALL MODE SELECTION
E W A13 - A0 (hex) MODE I/O NOTES
L
H
0E38 31C7 03E0 3C1F 303F 0FC0 0E38 31C7 03E0 3C1F 303F 0C63
Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL
Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z
l, m
L
H
l, m
Note l:
The six consecutive addresses must be in the order listed. W must be high during all six consecutive E controlled cycles to enable a nonvolatile cycle. Note m: While there are 15 addresses on the STK11C88, only the lower 14 are used to control software modes.
SOFTWARE STORE/RECALL CYCLEn, o
STK11C88-25 NO. SYMBOLS PARAMETER MIN
(VCC = 5.0V 10%)
STK11C88-45 UNITS MAX MIN MAX
26 27 28 29 30
tAVAV tAVELn tELEHn tELAXn tRECALL
n
STORE/RECALL Initiation Cycle Time
25 0 20 20 20
45 0 30 20 20
ns ns ns ns
s
Address Set-up Time Clock Pulse Width Address Hold Time
RECALL Duration
Note n: The software sequence is clocked on the falling edge of E controlled READs without involving G (double clocking will abort the sequence). See application note: MA0002 http://www.simtek.com/attachments/AppNote02.pdf. Note o: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlledo
tAVAV ADDRESS
27 ADDRESS #1 26
tAVAV
ADDRESS #6
26
tAVEL E
tELEH
28
tELAX
23 30 / tRECALL
29
tSTORE DQ (DATA OUT)
DATA VALID DATA VALID
HIGH IMPEDANCE
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STK11C88 nvSRAM OPERATION
The STK11C88 is a versatile memory chip that provides several modes of operation. The STK11C88 operates like a standard 32K x 8 SRAM. A 32K x 8 array of non-volatile storage elements shadow the SRAM. SRAM data can be copied to non-volatile memory or non-volatile data can be recalled to the
SRAM.
SOFTWARE NONVOLATILE STORE
The STK11C88 software STORE cycle is initiated by executing sequential READ cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. To initiate the software STORE cycle, the following READ sequence must be performed:
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0E38 (hex) 31C7 (hex) 03E0 (hex) 3C1F (hex) 303F (hex) 0FC0 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE cycle
NOISE CONSIDERATIONS
Note that the STK11C88 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1F connected between Vcc and Vss, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems.
SRAM READ
The STK11C88 performs a READ cycle whenever E and G are low and W is high. The address specified on pins A0-14 determines which of the 32,768 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high.
The software sequence must be clocked with E controlled READs. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation.
SRAM WRITE
A WRITE cycle is performed whenever E and W are low. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of READ operations must be performed:
1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0E38 (hex) 31C7 (hex) 03E0 (hex) 3C1F (hex) 303F (hex) 0C63 (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL cycle
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STK11C88
Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the Nonvolatile Elements. The nonvolatile data can be recalled an unlimited number of times.
HARDWARE PROTECT
The STK11C88 offers hardware protection against inadvertent STORE operation during low-voltage conditions. When VCC < VSWITCH, all software STORE operations are inhibited.
LOW AVERAGE ACTIVE POWER
The STK11C88 draws significantly less current when it is cycled at times longer than 50ns. Figure 2 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Figure 3 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK11C88 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the Vcc level; and 7) I/O loading.
POWER-UP RECALL
During power up, or after any low-power condition (VCC < VRESET), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the STK11C88 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected either between W and system VCC or between E and system VCC.
100
100
Average Active Current (mA)
Average Active Current (mA)
80
80
60
60 TTL CMOS 20
40 TTL 20 CMOS 0 50 100 150 Cycle Time (ns) 200
40
0 50 100 150 Cycle Time (ns) 200
Figure 2: ICC (max) Reads
Figure 3: ICC (max) Writes
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STK11C88
BEST PRACTICES
nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: * The non-volatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer's sites will sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product's firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, etc. should always program a unique NV pattern (e.g., complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. * Power up boot firmware routines should rewrite the nvSRAM into the desired state. While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, etc.).
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STK11C88
ORDERING INFORMATION
STK11C88 - N F 25 I TR
Packaging Option
Blank = Tube TR = Tape and Reel
Temperature Range
Blank = Commercial (0 to 70C) I = Industrial (-40 to 85C)
Access Time
25 = 25ns 45 = 45ns
Lead Finish (Lead-Free Only)
F = 100% Sn (Matte Tin)
Package
S=Plastic 28-pin 330 mil SOIC N=Plastic 28-pin 300 mil SOIC
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STK11C88
Ordering Codes
Part Number STK11C88-SF25 STK11C88-SF45 STK11C88-NF25 STK11C88-NF45 STK11C88-SF25TR STK11C88-SF45TR STK11C88-NF25TR STK11C88-NF45TR STK11C88-SF25I STK11C88-SF45I STK11C88-NF25I STK11C88-NF45I STK11C88-SF25ITR STK11C88-SF45ITR STK11C88-NF25ITR STK11C88-NF45ITR Description 5V 32Kx8 SoftStore nvSRAM SOP28-330 5V 32Kx8 SoftStore nvSRAM SOP28-330 5V 32Kx8 SoftStore nvSRAM SOP28-300 5V 32Kx8 SoftStore nvSRAM SOP28-300 5V 32Kx8 SoftStore nvSRAM SOP28-330 5V 32Kx8 SoftStore nvSRAM SOP28-330 5V 32Kx8 SoftStore nvSRAM SOP28-300 5V 32Kx8 SoftStore nvSRAM SOP28-300 5V 32Kx8 SoftStore nvSRAM SOP28-330 5V 32Kx8 SoftStore nvSRAM SOP28-330 5V 32Kx8 SoftStore nvSRAM SOP28-300 5V 32Kx8 SoftStore nvSRAM SOP28-300 5V 32Kx8 SoftStore nvSRAM SOP28-330 5V 32Kx8 SoftStore nvSRAM SOP28-330 5V 32Kx8 SoftStore nvSRAM SOP28-300 5V 32Kx8 SoftStore nvSRAM SOP28-300 Access Times 25 ns access time 45 ns access time 25 ns access time 45 ns access time 25 ns access time 45 ns access time 25 ns access time 45 ns access time 25 ns access time 45 ns access time 25 ns access time 45 ns access time 25 ns access time 45 ns access time 25 ns access time 45 ns access time Temperature Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial
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STK11C88 Package Drawings
28 - Pin 300 mil SOIC
0.292 7.42 0.300 7.59
(
)
0.400 10.16 0.410 10.41
(
)
Pin 1 Index
.050 (1.27) BSC 0.701 17.81 0.711 18.06
(
)
0.097 2.46 0.104 2.64
(
)
0.090 2.29 0.094 2.39
(
)
0.014 0.35 0.019 0.48
(
)
0.005 0.12 0.012 0.29
(
)
DIM = INCHES DIM = mm MIN MAX
0.009 0.23 0.013 0.32
(
)
0.024 0.61
0 8
(
)
MIN ( MAX)
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STK11C88
28 - Pin 330 mil SOIC
0.713 0.733
( 18.11 ) 18.62
0.112 (2.845)
0.004 (0.102)
0.020 0.014
( 0.508 ) 0.356
0.050 (1.270) 0.103 0.093
( 2.616 ) 2.362
0.336 0.326
( 8.534 ) 8.280
Pin 1
0.477 0.453
( 12.116 ) 11.506
0.014 0.008
( 0.356 ) 0.203
0.044 0.028
10 0
( 1.117 ) 0.711
DIM = INCHES DIM = mm
MIN MAX
MIN ( MAX )
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STK11C88
Document Revision History
Revision 0.0 0.1 0.2
Date December 2002 September 2003 March 2006 February 2007
Summary Removed 20 nsec device Added lead free lead finish Removed 35ns device, Removed Leaded Lead Finish, Removed DIP packages. Add fast power-down slew rate information Add Tape & Reel Ordering Options Add Product Ordering Code Listing Add Package Outline Drawings Reformat Entire Document extend definition of tHZ (#7) update fig. SRAM READ CYCLE #2, SRAM WRITE CYCLE #1, Note l and Note n to clarify product usage Page 4: in SRAM Read Cycles #1 & #2 table, revised description for tEHQZ and changed Symbol #2 to tELEH for Read Cycle Time; updated SRAM Read Cycle #2 timing diagram and changed title to add G controlled. Page 11: added best practices section. Page 13: added access times column to the Ordering Codes.
0.3
July 2007
0.4
2.0
January 2008
SIMTEK STK11C88 Datasheet, January 2008 Copyright 2008, Simtek Corporation. All rights reserved. This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other form or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein constitutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right.
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